Welcome back to part four of our video series on common mistakes in flyback power supplies and how to fix them. In this video, we'll look at two more issues, one regarding layout and the other dealing with stability. A poor layout can ruin a perfectly good power supply design. Take for example the 200 millowatt PSR flyback converter shown here. This supply works fine at no load, but when load is applied, the output goes out of regulation and the supply switches irradically. After inspecting the current send signals shown in the scope image, undesirable voltage spikes can be seen on the waveform. 

The large positive spike is blocked by the leading edge blanking time, but the large negative spike exceeds the maximum negative voltage rating for the current sense pin. This can inject currents into the substrate and cause erratic behavior or even device failure. The PCB is routed on two layers, as shown on left. The majority of the routing is on the bottom layer and primary ground, labeled PNG, is also poured on the bottom layer. The islands of unconnected PNG on the bottom layer, one up here and one down here, are connected together by a trace on the top layer. This long trace here. 

The current sense and primary current return path is shown by the thick curved arrows. What is wrong with this layout? With the very segmented P ground on the bottom layer, the switching current can only return to the bulk capacitor through the very long power ground trace on the top layer. This long trace introduces an inductance to the return path for the switching currents. The controller P ground connection for U1 is in the middle of the trace on the top layer. When the switch turns off, this inductions introduces a large negative spike on this trace. 

How can this layout be improved to eliminate the noise on this current sense? Here is an improved layout. The components on the bottom side were moved so that the current sense resistor R4 is closer to the P ground connections of the input capacitor C1. This reduces the inductance in the return path. The controller U1 is placed away from the noisy return path of the switching currents. P ground is flooded in the dead space on both the bottom and top layers, and then stitched together with vias near intruding traces. This minimizes ground noise and provides some shielding that helps spread the heat as well. 

PCB layout is a complex topic with many subtleties, but following a few simple rules can help reduce parasitics elements and improve the performance of your power supply. First, reduce parasitics inductances by keeping the current loops as small as possible. use ground planes under your signal and power traces whenever possible. Place IC filter capacitors as close to the IC pens as possible. 

Second, reduce parasitics capacitance by minimizing the cross-sectional area of the switch node and the grounding of heat sinks. Cross traces on adjacent layers orthogonally, which not only reduces parasitic capacitance, but prevents inductive currents from coupling in your traces. 

Third, reduce parasitics resistance by placing your power components as close as possible. Make sure your high current return pass are as short as possible. Use wide etches on high current paths to reduce trace impedance and improve efficiency. Finally, mitigate system noise by avoiding high switching currents through signal ground. Minimize trace lengths between resistor dividers, avoid putting ICs under the transformer since magnetic coupling can cause circuit misbehavior. 

Compensating an isolated power supply is not as straightforward as a simple buck regulator. The commonly used TL431 plus optocoupler circuit provides a different response from an op amp air amplifier. Consider our previous example of the 24 volt 36 watt flyback shown here, which has the loop response shown in this plot. The bandwidth is 6.2 kilohertz and the phase margin is only 44 degrees. How can the phase margin be increased? 

You may be tempted to put a resistor in series with C 14, hoping to implement a type II compensator and introduce a zero into the loop. If you tried this, you would undoubtedly be perplexed by the results. To get a better understanding of the effects of the components in the TL431 circuit, let's see what happens when we change one value at a time, and then we'll look at the math to understand why it happened. 

First consider what happens when we change the value of C 14 and increase it. This capacitor looks like an integrating capacitor, so it may seem that increasing this capacitor will lower the gain curve but preserve the shape of the phase plot. This animation shows how the gain and phase curves change when C 14 is increased from 10 nanofarads to 56 nanofarads. The crossover frequency remain 6.2 kilohertz, but the phase margin is increased to 56 degrees. Notice that the gain is reduced at lower frequencies, but the shape of the gain curve does not change above 10 kilohertz. Increasing this capacitor also provides a modest increase in phase above 200 Hertz. 

Next consider the effect of changing the value of R10. This animation shows the effects of increasing R10 from 300 ohms to 1,200 ohms. Notice that the phase plot didn't change significantly. The magnitude of the gain is reduced by 12 DB across the entire frequency range, but the shape of the gain curve did not change. Using 1,200 ohms, the crossover frequency is reduced to 2 kilohertz and the phase margin is now 72 degrees. The loop now has a large amount of gain and phase margin. 

Here we have a model for analyzing the frequency response of the TL431 optocoupler circuit, where we are interested in the small signal gain from V out to feedback. Notice here are two paths from V out to the optocoupler. The outer loop is the one that we are most familiar with in non-isolated power supplies. However, perturbations on V out also create an inner loop through the pull up resistor R1 of the optocoupler. The presence of this inner loop causes the frequency response of the circuit to be drastically different than that of the outer loop alone. 

On the top right, we have the equations and plot of the gain for the case where R4 is shorted. The gain is the product of two terms. The first term is the gain from the voltage across R1 to feedback, which represents the gain of the optocoupler. The gain of this section is determined by R1, R6, and the optocoupler CTR. Changing any of these values will allow us to add or take away gain to the loop, but there are limits to how much gain we can attenuate. 

Remember our previous discussion on current starving the optocoupler? The bandwidth of the optocoupler also introduces a pole into the response. The second term is the gain from V out to the voltage across R1. This term has a pole at the origin and a single 0 set by the values of R3 and C1. Notice that the gain of this term goes to 0 DB above the zero frequency. Increasing the value of C1 simply pushes the zero to a lower frequency, which will boost the phase but does not attenuate the gain. This explains the results seen in our example. 

Now let's see what happens when R4 is introduced. The new equations and gain plot are shown on bottom right. The response of the first term does not change. The second term has a pole at the origin but the location of the 0 is now determined by C1 and the sum of R3 and R4. Adding R4 increases the mid band gain, but does not introduce an additional 0. In most cases R4 provides no additional benefit.